The invention relates to a fabrication method for a semiconductor substrate made of a semiconductor material with spatially etched structures. The invention furthermore relates to a semiconductor substrate with a device for etching a spatial structure in the semiconductor substrate.
Dynamic memory cells usually have a storage capacitance reaching into a depth of a substrate and switching elements disposed at the surface of the semiconductor substrate. The capacitance reaching into the depth is disposed in so-called trenches that have previously been etched into the surface of the semiconductor substrate with the aid of an etching step. In this case, the trench is projected into the depth as a projection of a two-dimensional masking, so that generally hemispherical or cylindrical structures are produced. In this case, the value of the trench capacitance is usually determined by the depth and periphery of the structure, since the area thereby formed is crucial.
Memory circuits, in particular, are constructed particularly compactly, i.e. with the smallest possible area. Therefore, the extent of the trench structure at the semiconductor surface should be as small as possible, since switching and control structures likewise have to occupy space there in addition to the trench structure. However, the depth of the trench structure is limited by the process used. As a result, the total size of the trench, and thus the storage capacitance of the capacitor thereby formed, is limited since the size is essentially determined by the projection of the etching opening into the depth. It is possible to increase the capacitance if the trench structure is enlarged. However, this should be done as far as possible without enlarging the surface opening, in order not to increase the total area for a memory cell. The fabrication of more complicated three-dimensional structures which reach into the depth of the semiconductor material and whose extent is larger than the surface opening on the surface of the substrate has not been possible heretofore.
It is accordingly an object of the invention to provide a fabrication method and an apparatus for fabricating a spatial structure in a semiconductor substrate that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type, which can be used to fabricate spatial structures in a semiconductor substrate, with the intention that the extent of the structure on the semiconductor surface is as small as possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating spatially etched structures in a semiconductor substrate made of a semiconductor material. The method includes producing a depth structure in the semiconductor substrate proceeding from a surface of the semiconductor substrate, applying an etching-resistant layer in a collar region of a sidewall of the depth structure resulting in the sidewall covered with the etching-resistant layer being substantially etch resistant during subsequent etching steps, and forming a potential field in the semiconductor substrate around the depth structure. A spatial structure is etched with an aid of an etchant introduced into the depth structure. The etching proceeds from a region of the depth structure that is not covered by the etching-resistant layer. The etchant is chosen such that an etching direction is dependent on the potential field, and a form of the spatial structure is also dependent on the potential field.
A first aspect of the present invention provides a fabrication method for a semiconductor substrate made of a semiconductor material that has spatially etched structures lying in the semiconductor substrate, in particular trench structures for semiconductor memory cells. In the fabrication method, first the depth structure, e.g. a trench, is produced in the surface of the semiconductor substrate. A depth structure is understood to be a structuring of the semiconductor substrate that reaches into the depth of the substrate proceeding from a surface of the substrate. An etching-resistant layer is deposited into the depth structure in a collar region of the sidewall of the depth structure, so that that region of the sidewall which is covered with the etching-resistant layer is essentially not etched during subsequent etching steps. Afterward, an etchant is introduced into the depth structure and a potential field is applied in the semiconductor substrate. A spatial structure is etched proceeding from a region of the trench that is not covered by the etching-resistant layer, the spatial structure being dependent on the potential field.
The fabrication method according to the invention has the advantage that an etchant whose etching direction is dependent on a potential field can be introduced into deeper regions of the semiconductor substrate via the depth structure. Since a sidewall of that region of the depth structure which is preferably near the surface is protected from the etchant by the etching-resistant layer in such a way that, in this region, the sidewalls of the depth structure are not altered by the etchant, the etching takes place only in a lower part of the depth structure, which part is situated deep within the semiconductor substrate with respect to the surface. In this way, it is possible to achieve dimensions of the spatial structure, in particular of its lateral, i.e. surface-parallel, extent, which are considerably larger than the original extent of the corresponding depth structure. In particular the use of an etchant whose etching rate can be influenced by a potential field makes it possible to determine the final extent, form and direction of the spatial structure.
Such a spatial structure within a semiconductor substrate can then be used to form, e.g. in semiconductor memories, a capacitor structure with a high capacitance without having to increase the area at the surface of the semiconductor substrate of the capacitor structure. The area that is crucial for the capacitance may be the entire interface of such a structure within the substrate. The size of the depth structure and a length of the etching-resistant layer on the sidewall of the depth structure can be used to determine how deep the spatial structure is to lie within the semiconductor substrate and what dimensions it is to have in the vertical direction. As a result, it is possible to dispose the spatial structure at a sufficient distance from the surface of the semiconductor substrate so that the functionality of electronic circuits disposed at the surface remains essentially uninfluenced.
In a preferred embodiment, it is provided that a first etchant is used during the etching of the spatial structure, as a result of which the semiconductor material is etched into a porous (spongy) form. In a subsequent etching step, the porous (spongy) semiconductor material can be etched selectively with respect to the original semiconductor material with the aid of a second etchant, so that the porous and/or spongy semiconductor material is completely or partially removed in a space region. By way of example, an etchant containing hydrofluoric acid (HF) is suitable as the first etchant. The etching of silicon with hydrofluoric acid can be influenced in a particularly suitable manner by a potential field or a current line field. In particular, in the event of the porous and/or spongy semiconductor material being only partially removed from the deep spatial structure, it is possible to use the porous semiconductor material for suitable electronic components, e.g. laser diodes.
The production of the depth structure into the surface of the semiconductor substrate is preferably carried out with the aid of an etching operation using a third etchant. As an alternative, however, it is also possible to produce such a depth structure with the aid of a mechanical method, e.g. a laser drilling method. Structures penetrating through the semiconductor substrate can also be provided.
In order to obtain structures of diverse configurations, it is possible to change the potential field during the etching of the spatial structure. In other words, the strength of the potential field and the direction of the potential field can be changed in order to obtain the desired configuration of the spatial structure.
It is preferably provided that the etching-resistant layer is formed on a sidewall of the depth structure only in an upper part that lies in the vicinity of the surface of the semiconductor substrate. As a result, there remains a sidewall of the depth structure in the lower part, i.e. from the side remote from the surface, without an etching-resistant layer, so that an etching operation with the aid of the etchant can commence there. In this way, it is possible to prescribe an elongate configuration of the spatial structure in a direction perpendicular to the surface direction as the initial state.
A further aspect of the present invention provides a semiconductor substrate with a device for etching a spatial structure in the semiconductor substrate. The semiconductor substrate has a depth structure, a sidewall of the depth structure having an etching-resistant layer at least in a region near the surface of the semiconductor substrate, in order to prevent etching by an etchant there. Electrodes are disposed on or in the semiconductor substrate, it being possible to apply a specific voltage potential to each of the electrodes, so that a potential field and a current line field exist in the semiconductor substrate in order to affect an etching operation in the depth structure. Preferably, the voltage potential can be varied.
Such a semiconductor substrate has the advantage that it is suitable for thus producing a spatial structure within a semiconductor substrate, the opening of the depth structure at the surface of the semiconductor substrate being as small as possible.
In accordance with an added feature of the invention, the electrodes are insulated from the semiconductor substrate for substantially preventing a current flow through the electrodes.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a fabrication method and an apparatus for fabricating a spatial structure in a semiconductor substrate, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.